1. Field of the Invention
The present invention is related to a method for manufacturing isolation structures and more particularly to a method for manufacturing shallow trench isolation (STI) structures.
2. Description of Related Art
As semiconductor technology advances, dimensions of the semiconductor devices have also continued miniaturizing. Accordingly, the isolation between devices becomes more important as the isolation can effectively prevent the neighboring devices from shortage. In recent years, the most popular method used in the industry is a shallow trench isolation (STI) structure process.
Generally, a shallow trench isolation (STI) structure process includes the following. A pad oxide layer and a patterned mask layer are formed sequentially on the substrate, and then by using the patterned mask layer as a mask, a portion of the substrate is removed to form a shallow trench. Next, a STI structure is formed by filling insulation material in the shallow trench. Thereafter, the pad oxide layer and the patterned mask layer are removed by etching. In the method mentioned above, the step of removing the pad oxide layer may also remove a portion of the STI structure. Particularly, an upper corner of the STI structure tends to be removed, so that a divot around the upper corner is generated. Thus, a tunnel oxide layer or a gate oxide layer subsequently formed on the upper corner of the STI structure is too thin, which has a side effect on the flash memory device.
In order to prevent the phenomenon of the corner thinning resulted from the formation of the tunnel oxide layer or the gate oxide layer mentioned above, one of the conventional solutions is to pull back the patterned mask layer. In detail, after the STI structure is formed, the patterned mask layer is pulled back, thereafter a thermal oxidation process is performed on the STI structure to repair damage and reduce stress. In other words, a portion of the patterned mask layer is etched, and therefore the patterned mask layer is pulled back relative to the periphery of the STI structure. Then, a space, formed as the patterned mask layer pulled back, is filled with insulation material used to form the STI structure. The insulation material filling the space serves as a buffer layer, and thus the damage to the upper corner of the STI structure, resulted from an etching process to the pad oxide layer, is reduced. Accordingly, the divot around the upper corner of the STI structure is prevented. Therefore, when the tunnel oxide layer or the gate oxide layer is formed on the STI structure, the tunnel oxide layer or the gate oxide layer may has an uniform thickness on the upper corner and bulk of the STI, and the phenomenon of the corner thinning is not observed.
In addition, with the continual miniaturization of the dimensions of the memory devices, a pull-back amount of the patterned mask layer in the memory region is also gradually reduced. However, before the gate oxide layer is formed, the etching amount of the periphery region in the memory device is usually larger than that of the memory region in the memory device during the wet etching process. Furthermore, the periphery region in the memory device is driven by a higher driving voltage. Therefore, the thickness of the high-voltage gate oxide layer is difficult to reduce, and the patterned mask layer in the periphery region faces the issues of an insufficient pull-back amount. In other words, the divot may be generated around the upper corner of the STI structure due to the exposure. Thus, the gate oxide layer formed on the STI structure has an issue of the corner thinning and growth in the divot. Hence, the characteristics and the reliability of the memory device are deteriorated greatly.